spraaq7a_C281x_to_C2833x.pdf

Application ReportSPRAAQ7AJuly 2008TMS320 x281x to TMS320 x2833x or 2823x MigrationOverviewLori Heustess.AEC C2000ABSTRACTThisapplicationreportdescribesdifferencesbetweentheTexasInstrumentsTMS320 x281x and the TMS320 x2833x and TMS320 x2823x Digital Signal Controllers(DSCs)to assist in application migration.While the main focus of this document ismigration from 281x to 2833x/2823x,you will also find this document useful if you areconsidering migrating in the reverse direction.Functions that are identical in bothdevices are not necessarily included.All efforts have been made to provide acomprehensive list of the differences between the two device groups in the 28xgeneration.Contents1Introduction.22Central Processing Unit(CPU).33Development Tools.34Package and Pinout.45Operating Frequency and Power Supply.46Power Sequencing.57SARAM.58Flash and OTP.69Boot ROM.710Clocks and System Control.911Peripherals.1212Interrupts.1913Errata Fixes.2014References.2115Version History.22List of Tables1SARAM Addresses.62Sector Configuration Per Device.63Boot Mode Selection.84Boot Loader Entry Points.85New,Renamed,and Removed Registers.96Available Control Peripherals.12728335 ePWM Compared to 281x Event Manager.13828335 eCAP Compared to 281x Event Manager.14928335 eQEP Compared to 281x Event Manager.1410New ADC Registers.1611New,Updated,and Removed XINTF Registers.1812New,Updated,and Removed McBSP Registers.1813Communication Peripherals.19SPRAAQ7AJuly 2008TMS320 x281x to TMS320 x2833x or 2823x Migration Overview1Submit Documentation Feedback1Introduction1.1AbbreviationsIThe TMS320 x281x,TMS320 x2833x,and TMS320 x2823x devices are members of the C2000 DigitalSignal Controller generation for use within embedded control applications.The TMS320 x2833x andTMS320 x2823x devices feature enhanced peripherals,a DMA module,and an XINTF with 32-bit data buscapabilities.In addition,the 2833x includes the 28x plus floating-point-unit central processing unit(CPU).These new peripherals enable the firmware engineer to effectively solve challenging control problems.For purposes of migration,these devices can be thought of in two groups:1.TMS320 x281x2.TMS320 x2833x and TMS320 x2823xAs the focus of this document is to describe the differences between the two device groups,thedescriptions are explained only to the extent of highlighting areas that require attention when moving anapplication from one device to the other.For a detailed description of features specific to each device,seethe device-specific data manuals and user guides available on the TI website at http:/.Thisapplication report does not cover the silicon exceptions or advisories that may be present on each device.Consult the following silicon errata for specific advisories and workarounds:TMS320F2810F2811F2812TMS320C2810C2811C2812 DSP Silicon Errata(SPRZ193)TMS320R2811 and TMS320R2812 DSP Silicon Errata(SPRZ226)TMS320F280 x,TMS320C280 x,and TMS320F2801x DSP Silicon Errata Silicon Errata(SPRZ171)Note:Always refer to the TMS data manual for information regarding any electrical specifications.The following abbreviations are used in this document:281x:ReferstotheTMS320 x281xdevices.Forexample,TMS320F2810,TMS320F2811,TMS320F2812,TMS320C2810,TMS320C2811,TMS320C2812,TMS320R2811 and TMS320R2812.2833x:Refers to the TMS320 x2833x devices.For example,TMS320F28335,TMS320F28334 andTMS320F28332.2823x:Refers to the TMS320 x2823x devices.For example,TMS328F28235,TMS320F28234 andTMS320F28232.C28x+FPU refers to the C28x plus floating point unit.CCS refers to Code Composer Studio software.For a full list of devices currently available within the 281x and 2833x/2823x families,see the TI website.C2000,Code Composer Studio are trademarks of Texas Instruments.All other trademarks are the property of their respective owners.2TMS320 x281x to TMS320 x2833x or 2823x Migration OverviewSPRAAQ7AJuly 2008Submit Documentation Feedback2Central Processing Unit(CPU)3Development TCentral Processing Unit(CPU)The 2833x devices are the first devices to include the C28x plus floating point unit CPU(C28x+FPU).C28x+FPU based controllers have the same 32-bit fixed-point architecture as TIs existing C28x DSCs,but also include a single-precision(32-bit)IEEE 754 floating point unit(FPU).It is a very efficient C/C+engine,enabling you to develop system control software and math algorithms using C/C+.No changes have been made to the existing:C28x InstructionsC28x PipelineC28x EmulationMemory Bus ArchitectureNew instructions to support floating point operations have been added as an extension to the standardC28x instruction set.This means code written for the C28x fixed-point CPU is 100%compatible with theC28x+FPU.The C28x+FPU latched overflow and underflow(LVF,LUF)flags are connected to theperipheral interrupt expansion(PIE)block.This makes debugging overflow and underflow issues mucheasier.For an introduction to the C28x+FPU,refer to the C28x FPU Primer(SPRAAN9)and theTMS320C28x Digital Signal Controller Plus Floating Point Unit online training from the TI website.The C28x+FPU architecture and instruction set are documented in the following two reference guides:TMS320C28x DSP CPU and Instruction Set Reference Guide(SPRU430).This document also appliesto the C28x+FPU.TMS320C28x Floating Point Unit and Instruction Set Reference Guide(SPRUEO2).This is asupplement to the TMS320C28x DSP CPU and Instruction Set Reference Guide(SPRU430).A new set of header files and peripheral examples are available for the 2833x and 2823x with the samestructure as the 280 x/2801x/2804x header files.Refer to C2833x/C2823x C/C+Header Files andPeripheral Examples(SPRC530).Since the peripherals on the 2833x and 2823x are identical,the headerfiles are shared by the two devices.In the header file package,the examples have been duplicated withone set enabling native floating point(2833x)and the other group setup to only generate fixed point code(2823x).The C28x+FPU on the 2833x is supported with a patch to Code Composer Studio 3.3.Currently the FPUregisters can be viewed within a Code Composer Studio watch window only.The 2833x GEL files includea function to automatically populate the watch window with the FPU registers.In future updates to CodeComposer Studio,the FPU registers will be added to a register window.Current C2000 emulation podswill work with the C28x+FPU.The compiler,assembler,and linker must be V5.0 or greater to take advantage of the 2833x hardwareFPU resources.As of this writing,the latest compiler is V5.0.1.Check Code Composer Studio updateadvisor for future updates.When building for native floating-point,you must use the correct run-timesupport library.When compiling with-float_support=fpu32 use the C28x FAST RTS Library(SPRC664)incombination with the standard rts2800_fpu32.lib or rts2800_fpu32_eh.lib supplied with the compiler.Note:To get the best native floating-point performance for math routines on the 2833x,use theC28x FPU Fast RTS Library(SPRC664).The C28x Fast RTS is a collection of optimizedfloating-point math functions for C programmers of the C28x with Floating-Point Unit.Designers of computationally intensive real-time applications can achieve execution speedsconsiderably faster than what are currently available without having to rewrite existing code.The functions listed in the features section are specifically optimized for the C28x+FPUcontrollers.SPRAAQ7AJuly 2008TMS320 x281x to TMS320 x2833x or 2823x Migration Overview3Submit Documentation Feedback3.1Migrating from IQMath to Native Floating-Point4Package and Pinout5Operating Frequency and Power SupplyPackage and PNote:To enable the compiler to generate native FPU instructions,you must tell it that you have aC28x device with a floating point unit.To do this,use the following compiler switches:-v28-float_support=fpu32In Code Composer Studio the fpu32 switch is under the advanced compiler options.You can not mix code built without the-float_support=fpu32 switch with code built with it.This is because the compiler calling conventions changed for floating point numbers.If youtry to mix the two the linker will issue an error indicating the object files are not compatible.Ifyou receive this error,first check that all libraries have been built with the same switch.Inparticular the runtime support library that comes with the compiler must be correct.Whencompiling with-float_support=fpu32 use the rts2800_fpu32.lib or rts2800_fpu32_eh.lib.If you have a project written in the IQmath format,and want to convert it to native floating-point then thefollowing steps need to be taken:1.Select FLOAT_MATH in the IQmath header file.The header file converts all IQmath function calls totheir floating-point equivalent.2.Convert the floating-point number to an integer when writing a floating-point number into a deviceregister.Likewise when reading a value from a register:it will need to be converted to float.In bothcases,this is done by multiplying the number by a conversion factor.For example to convert afloating-point number to IQ15,multiply by 32768.0 as shown below.#if MATH_TYPE=IQ_MATHPwmReg=(int16)_IQtoIQ15(Var1);#else/MATH_TYPE is FLOAT_MATHPwmReg=(int16)(32768.0L*Var1);#endifLikewise,to convert from an IQ15 value to a floating-point value,multiply by 1/32768.0 or0.000030518.0.3.Do the following to take advantage of the on-chip floating point unit:Use C28x codegen tools version 5.0.2 or later.Tell the compiler it can generate native C28x floating-point code.To do this,use the v28-float_support=fpu32 compiler switches.In Code Composer Studio the float_support switch is onthe advanced tab of the compiler options.Use the correct run-time support library for native 32-bit floating-point.For C code this isrts2800_fpu32.lib.For C+code with exception handling,use rts2800_fpu32_eh.lib.Consider using the C28x FPU Fast RTS library(SPRC664)to get a performance boost from mathfunctions such as sin,cos,div,sqrt,and atan.The Fast RTS library should be linked in before thenormal run-time support library.The 281x and 2833x/2823x are neither package nor pin-compatible.Any application being moved from281x to the 2833x or 2823x requires a new board layout to accommodate the changes in pinout andpackage.The required core voltage supply for the 281x devices depends on the operating frequency of the device.The 281x devices can operate up to 150 MHz with a core voltage of 1.9-V.At 135 MHz and below a 1.8-Vcore voltage is required.The 150 MHz 2833x/2823x devices require a 1.9-V core voltage and the 100MHz devices require a 1.8-V core voltage.Both the 281x and 2833x devices require a 3.3-V I/O supply.Note:Always refer to the TMS data manual for information regarding any electrical specifications.4TMS320 x281x to TMS320 x2833x or 2823x Migration OverviewSPRAAQ7AJuly 2008Submit Documentation Feedback6Power Sequencing7SARAMPower SequencingSee the following data manuals for the most recent detailed electrical specifications:TMS320F2810,TMS320F2811,TMS320F2812,TMS320C2810,TMS320C2811,TMS320C2812 DigitalSignal Processors Data Manual(SPRS174)TMS320F28335,TMS320F28334,TMS320F28332,TMS320F28235,TMS320F28234,TMS320F28232 Digital Signal Controllers Data Manual(SPRS439)The restrictions placed on power sequencing have been relaxed.For the 281x devices,the power sequencing requirements dictate that the VDDIOrail must begin its rampprior to the VDDrail.For 2833x/2823x devices,the VDDIOand VDDrail can instead ramp together.Forcustomers migrating their design from the 281x,the sequencing scheme used for the 281x devices canstill be applied to a 2833x/2823x device.See the appropriate data manual for each device for details related to power sequencing:TMS320F2810,TMS320F2811,TMS320F2812,TMS320C2810,TMS320C2811,TMS320C2812 DigitalSignal Processors Data Manual(SPRS174)TMS320F28335,TMS320F28334,TMS320F28332,TMS320F28235,TMS320F28234,TMS320F28232 Digital Signal Controllers Data Manual(SPRS439)This section highlights the major differences in the SARAM memory subsystem.Increased amount of SARAMOn the 281x 18K x 16 words of SARAM were available.On the 2833x/2823x up to 34K x 16 areavailable.Maximum SARAM block size 4K x 16The H0 SARAM block at 0 x3F8000 was split into two smaller memory blocks:L0 and L1.Themaximum size of an SARAM block is now 4K x 16.The smaller memory blocks on the 2833x/2823xmake it easier to partition code and data.If your code uses multiply and accumulate operations(MAC),for example,partition the opcode and two operands into three different memory blocks.This allows formaximum efficiency.SARAM blocks are dual-memory mappedMemory blocks L0,L1,L2 and L3 are all dual mapped into both high memory and low memory.Thedual mapping of the memory gives flexibility when partitioning code as required by the application.Thememory region in the upper 64K range is required when running 24x compatible code while the stackpointer(SP)can only access memory in the lower 64K.If the application is not porting 24x code,theneither memory map location can be used for either data or code.Keep in mind that the stack pointercan still only access the lower 64K range.SPRAAQ7AJuly 2008TMS320 x281x to TMS320 x2833x or 2823x Migration Overview5Submit Documentation Feedback8Flash and OTPFlash and OTPTable 1.SARAM AddressesMemory Address281x Memory Block2833x/2823x MemoryBlock(1)0 x00 8000 0 x00 8FFFL0L00 x00 9000 0 x00 9FFFL1L10 x00 A000 0 x00 AFFFN/AL20 x00 B000 0 x00 BFFFN/AL30 x00 C000 0 x00 CFFFN/AL4(2)0 x00 D000 0 x00 DFFFN/AL5(2)0 x00 E000 0 x00 EFFFN/AL6(2)0 x00 F000 0 x00 FFFFN/AL7(2)0 x3F 8000 0 x3F 8FFFL0 MirrorH00 x3F 9000 0 x3F 9FFFL1 Mirror0 x3F A000 0 x3F AFFFN/AL2 Mirror0 x3F B000 0 x3F BFFFN/AL3 Mirror(1)Note that not all of the SARAM blocks are available on all family derivatives.Refer to thedevice-specific data sheets.(2)DMA accessible block.1 wait state in program space.Note:The H0 memory block of the 281x now has L0 and L1 dual mapped in its place.Therefore,ifcode compiled for 281x is loaded without changing the memory map,data or code that wasoriginally in the H0 memory region 0 x3F 8000 0 x3F 9FFF may be overwritten by the dataor code from the L0 and L1 memory blocks.Wait statesOn 281x devices,all SARAM blocks are 0 wait state in both program and data space.On the2833x/2823x devices,blocks L4,L5,L6 and L7 are 0 wait for accesses that use the data bus and 1wait for accesses that use the program bus.A program bus access occurs when an instruction opcodeis fetched or when program-space indirect or direct addressing is used.Instructions that useprogram-space addressing to access an operand include MAC,DMAC,QMACL,IMACL,PREAD andPWRITE.For example,MAC uses program-space addressing via the XAR7 register.This instructionsees a decrease in performance if the operand pointed to by XAR7 is in L4-L7.L4-L7 should beallocated for data space accesses before they are used for program code or data accessed viaprogram-space addressing.DMA accessible SARAMThe L4-L7 memory blocks can be used as a source and/or destination for each of the six channels.Onthe 281