5.Large+and+Fast++Exploiting+Memory+Hierarchy.pptVIP免费

ComputerComputerOrganization&DesignOrganization&Design——TheHardware/SoftwareInterfaceTheHardware/SoftwareInterface25/1/271PresentationOutlinePresentationOutlineRandomAccessMemoryanditsStructureMemoryHierarchyandtheneedforCacheMemoryTheBasicsofCachesCachePerformanceandMemoryStallCyclesImprovingCachePerformanceMultilevelCachesLargearraysofstoragecellsVolatilememoryHoldthestoreddataaslongasitispoweredonRandomAccessAccesstimeispracticallythesametoanydataonaRAMchipOutputEnable(OE)controlsignalSpecifiesreadoperationWriteEnable(WE)controlsignalSpecifieswriteoperation2n×mRAMchip:n-bitaddressandm-bitdataRandomAccessMemoryRandomAccessMemoryRAMAddressDataOEWEnmMemoryTechnologyMemoryTechnologyStaticRAM(SRAM)forCacheRequires6transistorsperbitRequireslowpowertoretainbitDynamicRAM(DRAM)forMainMemoryOnetransistor+capacitorperbitMustbere-writtenafterbeingreadMustalsobeperiodicallyrefreshedEachrowcanberefreshedsimultaneouslyAddresslinesaremultiplexedUpperhalfofaddress:RowAccessStrobe(RAS)Lowerhalfofaddress:ColumnAccessStrobe(CAS)StaticRAMStorageCellStaticRAMStorageCellStaticRAM(SRAM):fastbutexpensiveRAM6-TransistorcellTypicallyusedforcachesProvidesfastaccesstimeCellImplementation:Cross-coupledinvertersstorebitTwopasstransistorsRowdecoderselectsthewordlinePasstransistorsenablethecelltobereadandwrittenTypicalSRAMcellVccWordlinebitbitDynamicRAMStorageCellDynamicRAMStorageCellDynamicRAM(DRAM):slow,cheap,anddensememoryTypicalchoiceformainmemoryCellImplementation:1-Transistorcell(passtransistor)Trenchcapacitor(storesbit)BitisstoredasachargeoncapacitorMustberefreshedperiodicallyBecauseofleakageofchargefromtinycapacitorRefreshingforallmemoryrowsReadingeachrowandwritingitbacktorestorethechargeTypicalDRAMcellWordlinebitCapacitorPassTransistorTypicalDRAMPackagingTypicalDRAMPackaging24-pindualin-linepackagefor16Mbit=2224memory22-bitaddressisdividedinto11-bitrowaddress11-bitcolumnaddressI...