8.4ADC0809VHDL控制程序见随书所附光盘中文件：ADC0809VHDL程序与仿真。--文件名：ADC0809.vhd--功能：基于VHDL语言，实现对ADC0809简单控制--说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟信号，这里由FPGA的系--统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。--最后修改日期：2004.3.20libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityADC0809isport(d:instd_logic_vector(7downto0);--ADC0809输出的采样数据clk,eoc:instd_logic;--clk为系统时钟，eoc为ADC0809转换结束信号clk1,start,ale,en:outstd_logic;--ADC0809控制信号abc_in:instd_logic_vector(2downto0);--模拟选通信号abc_out:outstd_logic_vector(2downto0);--ADC0809模拟信号选通信号q:outstd_logic_vector(7downto0));--送至8个并排数码管信号endADC0809;architecturebehavofADC0809istypestatesis(st0,st1,st2,st3,st4,st5,st6);--定义各状态的子类型signalcurrent_state,next_state:states:=st0;signalregl:std_logic_vector(7downto0);--中间数据寄存信号signalqq:std_logic_vector(7downto0);begincom:process(current_state,eoc)--规定各种状态的转换方式begincasecurrent_stateiswhenst0=>next_state<=st1;ale<='0';start<='0';en<='0';whenst1=>next_state<=st2;ale<='1';start<='0';en<='0';whenst2=>next_state<=st3;ale<='0';start<='1';en<='0';whenst3=>ale<='0';start<='0';en<='0';ifeoc='1'thennext_state<=st3;--检测EOC的下降沿elsenext_state<=st4;endif;whenst4=>ale<='0';start<='0';en<='0';ifeoc='0'thennext_state<=st4;--检测EOC的上升沿elsenext_state<=st5;endif;whenst5=>next_state<=st6;ale<='0';start<='0';en<='1';whenst6=>next_state<=st0;ale<='0';start<='0';en<='1';regl<=d;whenothers=>next_state<=st0;ale<='0';start<='0';en<='0';endcase;endprocess;clock:process(clk)--对系统时钟进行分频，得到ADC0809转换工作时钟beginifclk'eventandclk='1'thenqq<=qq+1;--在clk1的上升沿，转换至下一状态ifQQ="01111111"THENclk1<='1';current_state<=next_state;elsifqq<="01111111"thenclk1<='0';endif;endif;endprocess;q<=regl;abc_out<=abc_in;endbehav;
