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1ComputerComputerOrganization&DesignOrganization&Design——TheHardware/SoftwareInterfaceTheHardware/SoftwareInterface25/1/271Theprocessor2ChapterFour:TheprocessorChapterFour:Theprocessor4.1Introduction4.2LogicDesignConventions4.3Buildingadatapath4.4ASimpleImplementationScheme4.5AnOverviewofPipelining4.6PipelinedDatapathandControl4.7DataHazards:ForwardingversusStalling4.8ControlHazards4.9Exceptions4.10ParallelismandAdvancedInstruction-LevelParallelism4.11RealStuff:theAMDOpteronX4Pipeline25/1/2723We‘lllookatanimplementationoftheMIPSSimplifiedtocontainonly:memory-referenceinstructions:lw,swarithmetic-logicalinstructions:add,sub,and,or,sltcontrolflowinstructions:beq,jAnOverviewoftheimplementationForeveryinstruction,thefirsttwostepareidenticalFetchtheinstructionfromthememoryDecodeandreadtheregistersNextstepsdependontheinstructionclassMemory-referenceArithmetic-logicalbranches4.1Introduction4.1IntroductionWhataresteps?HowmanyFUN.?25/1/2734We'rereadytolookatanimplementationoftheMIPSinstructionsetSimplifiedtocontainonlyarithmetic-logicinstructions:add,sub,and,or,sltmemory-referenceinstructions:lw,swcontrol-flowinstructions:beq,jImplementingMIPSImplementingMIPSoprsrtoffset6bits5bits5bits16bitsoprsrtrdfunctshamt6bits5bits5bits5bits5bits6bitsR-FormatI-Formatopaddress6bits26bitsJ-Format5High-levelabstractviewoffetch/executeimplementationusetheprogramcounter(PC)toreadinstructionaddressfetchtheinstructionfrommemoryandincrementPCusefieldsoftheinstructiontoselectregisterstoreadexecutedependingontheinstructionrepeat…ImplementingMIPS:theImplementingMIPS:theFetch/ExecuteCycleFetch/ExecuteCycleRegistersRegister#DataRegister#DatamemoryAddressDataRegister#PCInstructionALUInstructionmemoryAddress6AnabstractviewoftheAnabstractviewoftheimplementationofMIPSimplementationofMIPS25/1/2767Overview:ProcessorOverview:ProcessorImplementationStylesImplementationStylesSingleCycleperformeachinstructionin1clockcycleclockcyclem...